An edge-triggered flip-flop is a component commonly used in microelectronics to store a binary value or a “state.” FIG. 1 schematically illustrates the general architecture of such a flip-flop according to the prior art. As seen in this figure, a common way of making the flip-flop is to join together two latching memories 1a, and 1b, (“latches”), called respectively master flip-flop and a slave flip-flop, each clocked by two phases of a clock signal CPn corresponding to an inverted clock signal and CPi corresponding to a copy of the clock signal.
A latching memory may be a bistable structure including two inverters connected in such a way that the first inverter is looped back to its input through the second. Inverters controlled by two clock phases may be used to render the bistable structure either transparent to the data item coming from outside, or opaque for this data item. In this case, the bistable structure stores and copies the previous data item.
Such an inverter, illustrated in FIGS. 1a and 1b, may be designated as a double-phase controlled inverter. As seen in these figures, for example, in the configuration illustrated in FIG. 1a, these clock-controlled inverters respectively include, on the one hand two p-channel metal oxide semiconductor PMOS transistors Tr1 and Tr2 in series, one controlled by the data item D and the other by a phase of the clock Cpi and, on the other hand, two n-channel metal oxide semiconductor (NMOS) transistors Tr3 and Tr4, in series one controlled by the same data signal D and the other by a phase CPn inverse to the previous phase of the clock.
Two alternatives to such a device may also be used. These two alternatives are illustrated in FIGS. 2a and 2b. In FIG. 2a, the inverter comprises two PMOS transistors Tr5 and Tr6 in series, one controlled by a clock phase CPi, the other by the data signal D, and an NMOS transistor Tr7 controlled by the same data signal. This is a half-controlled PMOS inverter. In FIG. 2b, the inverter comprises two NMOS transistors Tr8 and Tr9 in series, one controlled by a phase of the clock CPi, and the other by the data signal D, and a PMOS transistor Tr9 controlled by the same data signal. This is a half-controlled NMOS inverter. These two alternatives illustrated in these FIGS. 2a and 2b) require only one clock phase.
Referring to FIG. 3 which illustrates the architecture of a flip-flop, the clock signals CPn and CPi are constructed by passing successively through a first inverter (CPn) and then through a second inverter (CPi). It may be common to regenerate the phase CPi copying the clock rather than to directly use the clock signal as input to decrease its load capacity. This passage through two inverters increases the circuit's energy consumption related to the activity of the clock, and may give rise to a delay between the clock signal and the data.
Moreover, the testability obligations for integrated circuits lead to the systematic use of a debugging multiplexer at the flip-flop input to transform, during the test, a set of flip-flops into a shift register (“scan shift register”), and to render accessible, in a static and macroscopic manner, the internal states of the circuit. This is the purpose of the multiplexer of the shift register whose selection signal is the signal TE.
It may be possible for the two functions of controlled inverter and of test multiplexer to be merged in a single complimentary oxide semiconductor (CMOS) stage. Currently, technologies for manufacturing electronic components may make it possible to obtain high-speed integrated circuits. Such is the case for the technique described in the publication “Resonant-Clock latch-based-design”, IEEE journal of solid-state circuits, vol 43, No. 4, Apr. 2008, which describes a flip-flop architecture making it possible to obtain, in particular, faster latching memories (“latches”). Accordingly, as illustrated in FIGS. 4 and 5, which illustrate two embodiments of latch transparent respectively on a high phase and a low phase of a clock signal CP, a latching memory with single clock signal preceded by two half-controlled inverters in series are placed in series. Indeed, with a half-controlled inverter disabling only one data phase when the clock is deactivated, it may be necessary to connect two of them in series to render the set opaque for the two data phases. It may thus be possible to make a latching memory with a single clock signal transparent on a single clock edge by abutting two latches such as previously described: (L-latch Svensson) (H-latch Svensson).